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product overview the 25a power block is a non-isolated switch- ing power converter, providing up to 49.5w with an input range of 7-13.2v dc, a regulated output of 0.8-3.6v dc, and load current up to 25a at 1v output voltage. the power block is a synchronous buck converter. it has been implemented using a synchronous buck gate driver ic with co-packed control and synchronous mosfets and schottky diode. the output ? lter consists of 375nh induc- tance and 20f capacitance. features ? ? high ef? ciency (91% @12vin, 1.8vout) ? ? power block (25a, 7-13vin, 0.8-3.6vout, smt) ? ? input under-voltage lockout ? ? small footprint (0.5 [12.7] x 0.67 [17] x 0.42 [10.7]) ? ? no minimum load required ? ? low output ripple ? ? -20c to 70c operating temperature figure 1. block diagram (pending) thermal sensor output filter vout gnd 2.15k +5v vin pwm gnd temp +cs -cs oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 1 of 20 www.murata-ps.com www.murata-ps.com/support for full details go to www.murata-ps.com/rohs $ typical unit 25 a p o t ypical uni t
part number structure oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 2 of 20 www.murata-ps.com/support performance specifications summary and ordering guide root model output input ? ef? ciency ? dimensions vout (volts) iout (amps, max.) power (watts) vin nom. (volts) range (volts) iin, full load (amps) inches (mm) min. typ. oklp-x/25-w12-c ? 0.8-3.3 25 49.5 12 7-13.2 7.56 92% 93.5% 0.5 x 0.67 x 0.42 (12.7 x 17.02 x 10.7) / output voltage range 0.8-3.3vdc - x lga surface mount l power block p okami non-isolated pol ok c - rohs hazardous substance compliance c = rohs-6 (does not claim eu rohs exemption maximum rated output current in amps 25 - input voltage range 7-13.2vdc w12 ? typical at ta=+25c ? @vin=7v, vout=3.3v, iout=15a ? @vin=12v, vout=3.3v, iout=15a
oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 3 of 20 www.murata-ps.com/support 1. input requirements table 1.1. voltage: parameter notes min nom max units enable (pin 2) turn-on module 2.0 v turn-off module 0.8 vin (pin 1): operating 7 12 13.2 v absolute max 16.5 +5v (pin 10): operating 4.5 5 6 v under-voltage lockout, rising 4.1 under-voltage lockout, falling 3.0 pwm (pin 8): high 1 2.5 v pin 10 +0.3v v low 0.8 1. before the pwm signal is applied to pin #8 (pwm), ensure that +5v is applied to the gate driver ic supply (pin 10). otherwise, permanent damage may result to the unit. table 1.2. current: parameter notes min nom max units vin=7v, vout=3.3v, iout=15a (pin 1) 7.56 a vin=7v, vout=1.8v, iout=20a 6.335 a vin=12v, vout=1.8v, iout=20a 3.37 a +5v (pin 10) (switching at 500 khz) 30 40 ma 2. output requirements table 2.1. voltage: parameter notes min nom max units operating range 0.8 1.8 3.6 v table 2.2. current per phase: parameter notes min nom max units operating range 1.0vout 1 0 25 a 1.8vout 1 0 20 a 3.3vout 1 0 15 a 1. 7v to 12v input, switching at 500khz.
oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 4 of 20 www.murata-ps.com/support table 2.3. power/ef? ciency parameter notes min nom max units output power 49.5 w ef? ciency: 1.0v output at 25a, vin=7v 1, 2 88 90 % 1.0v output at 25a, vin=12v 86.5 89 % 1.8v output at 20a, vin=7v 90.5 93 % 1.8v output at 20a, vin=12v 89 91 % 3.3v output at 15a,vin=7v 93.5 95.5 % 3.3v output at 15a, vin=12v 92 93.5 % 1. 7v to 12v input, switching at 400khz, with 200 lfm at 55c 2. gate drive and controller losses are included. for the purpose of this calculation, controller loss is assumed to be 0.2w. table 2.4. capacitor parameter notes min nom max units input capacitance 1 60 f output capacitance 2, 3 20.1 f 1. 6*10f/16v/x7r 2. 2 x 10f, 0805, 6.3v, x7r + 1 x 0402, 0.1f, 16v, x7r 3. additional input and output capacitors are to be added externally as part of the buck regulator design. table 2.6. inductor parameter notes min nom max units inductance 323 380 437 nh dcr (25c) 1 0.665 0.7 0.735 m isat (125c) 35 a 1. see block diagram for dcr sense requirements. table 2.5. resistor parameter notes min nom max units output-to-gnd resistor 301 table 3. temperature sense parameter notes min nom max units bias current sourced from controller (into pin 7) 495 ua voltage at 25c (pin 7) 1.34 1.35 1.36 v temperature coef? cient (0 to 130 c) -4.4 mv / c
oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 5 of 20 www.murata-ps.com/support table 5.3. pinout pin # name function 1 vin input voltage for the mosfet 2 enable turn off module (enable < 0.8v), turn on module (enable > 2.0v) 3 +cs positive dcr sense 4 -cs negative dcr sense 5 vo output voltage 6,9 gnd ground for both input and output 7 temperature from temperature sense device on the power block for temperature sensing. 8 pwm 3.3v compliant pwm signal to the gate driver 10 +5v bias voltage for gate driver 5. mechanical 5.1. general single-board, designed for machine pick-n-place. footprint is 0.5 x 0.67 . maximum height is 0.48 . 4. dynamic load response: iout 50-100-50% nom settling time to within 2% of vout (see dynamic load response plots) table 5.2. parameter notes nom units dimensions 0.5x 0.67 x 0.42 inches 12.7x 17.02 x 10.7 mm weight 0.179 ounces 5.09 grams
figure 2. recommended footprint oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 6 of 20 www.murata-ps.com/support 5.4. mechanical speci? cations [3.35] 0.132 [10.16] 0.400 [5.08] 0.200 [13.21] 0.520 [13.41] 0.528 [8.76] 0.345 [6.604] 0.260 [17.52] 0.690 [2.06] 0.081 [1.52] 0.060 c l c l 87 9 10 (viewed through power block) 12345 6 recommended footprint c l 10x [2.74] 0.108 10x [1.96] 0.077
oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 7 of 20 www.murata-ps.com/support third angle projection 4.00 .157 11.92.2 .47.09 10.16 .400 13.40 .528 3.35 .132 all pins coplanar within .004" dimensions are in inches [mm] tolerances: 2 place .02 angles: 1 3 place .010 components shown are for reference only material: pins: copper alloy finish: (all pins) gold (5u"min) over nickel (50u" min) c l 17.0 .67 12.7 .50 .025 x 45 (pin #1 indicator) 10.7 .42 0.25 .010 min 9 10 6 7 5 34 8 2 1 k6* k1* pin #1 k5* 10x 1.60 .063 10x 2.29 .090 5.4. mechanical speci? cations, cont. figure 3. mechanical dimensions input/output connections pin function k point 1vin * 2 enable 3 cs+ 4 cs- 5 vout * 6 gnd * 7 temp 8 pwm 9 gnd 10 5v
oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 8 of 20 www.murata-ps.com/support 4.00 .157 6.4 .25 11.92.2 .47.09 1.59 40.4 2.00 .079 ref pick-up nozzle location 4.0-6.0mm 20.00 .787 pitch 23.8 .94 ref 7770235 shipping kit tape and reel with msl2 packaging (not shown) 200 units per reel tape and reel 330.2 13.00 point pickup .025 x 45 (pin #1 indicator) oblong holes along this edge pin #1 typ (orientation) pocket tape detail feed (unwind) direction .157 4.00 .059 (round) sprocket holes along this edge 1.50 44.0 1.73 tape and reel information (msl rating 2) figure 4. tape and reel
thermal sensor output filter vout gnd 2.15k +5v vin pwm gnd temp +cs -cs figure 5. block diagram oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 9 of 20 www.murata-ps.com/support 7. miscellaneous table 7.1. environmental parameter notes min nom max units temperature, operating, long-term 1 -5 - 55 c temperature, operating, short-term (72 hours) 2, 3 -20 70 c temperature, storage -40 - 125 c available air? ow (along either long or short side) 200 - - lfm altitude, operating 4 -500 - 10,000 feet relative humidity, operating, non-condensing 10 - 90 % msl rating 2 1. units component temperatures will not exceed vendors derating guidelines with up to 3 units operating side by side spaced 0.1 apart. 2. for single unit operation, component temperatures can exceed vendors derating guidelines, but will not exceed com- ponent max temperature ratings. 3. with up to 3 units operating side by side spaced 0.1 apart, component temperatures will not activate otp, and will not compromise reliability. 4. derate operating temperature 1c per 1000 feet of altitude above sea level. 6. block diagram for dcr sensing, there is a 2.15k resistor on the power block (between cs+ and output inductor as shown) to work with an external 0.22f capacitor (not supplied with the power block). the external c shown as across cs+ and cs- pins should be installed on the pcb. the r value in the rc network is the inductor dcr, used in the relation l/(dcr+pcb trace)=rc. (pcb trace equal 0.1m.)
oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 10 of 20 www.murata-ps.com/support table 7.2. reliability parameter notes min nom max units calculated mtbf 1 7.683 - mhrs service life 2-7-y ears 1. calculated according to bellcore or telcordia tr-ntw-000332 at 40c full-load. 2. calculated at 30 c. 7.3. parallel operation 2 or more units will be operated in parallel. current sharing function will be performed by the external pwm controller. 7.4. use of ceramic capacitors unit does not use any smt ceramic capacitors larger than 1210. 7.5. smt re? ow soldering guidelines the surface-mount re? ow solder pro? le shown below is suitable for sac305 type lead-free solders. this graph should be used only as a guideline. many other factors in? uence the success of smt re? ow soldering. since your produc- tion environment may differ, please thoroughly review these guidelines with your process engineers.
typical performance data 50 55 60 65 70 75 80 85 90 95 0 5 10 15 20 25 load curre nt (amps) ef?ciency (%) v in = 7v v in = 12v 50 55 60 65 70 75 80 85 90 95 0 5 10 15 20 25 load curre nt (amps) ef?ciency (%) v in = 7v v in = 12v maximum current temperature derating at sea level vout = 1v; vin = 7-13.2v maximum current temperature derating at sea level vout = 3.3v; vin = 7-13.2v maximum current temperature derating at sea level vout = 1.8v; vin = 7-13.2v 0 5 10 15 20 25 30 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 natural convection 1.0 m/s (200 lfm) output current (amps) ambient temperature (c) 0 5 10 15 20 25 30 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 natural convection 1.0 m/s (200 lfm) output current (amps) ambient temperature (c) 0 5 10 15 20 25 30 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 natural convection 1.0 m/s (200 lfm) output current (amps) ambient temperature (c) ef? ciency vs. line voltage and load current @ +55?c., 200 lfm (vout = 1.8v) ef? ciency vs. line voltage and load current @ +55?c., 200 lfm (vout = 3.3v) ef? ciency vs. line voltage and load current @ +55?c., 200 lfm (vout = 1.0v) 50 55 60 65 70 75 80 85 90 95 100 0 5 10 15 load curre nt (amps) ef?ciency (%) v in = 7v v in = 12v oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 11 of 20 www.murata-ps.com/support
typical performance data 0 5 10 15 20 25 60 65 70 75 80 85 90 95 100 load curre nt (amps) ef?ciency (%) 400khz 500khz 600khz 60 65 70 75 80 85 90 95 100 0 5 10 15 20 load curre nt (amps) ef?ciency (%) 400khz 500khz 600khz 60 65 70 75 80 85 90 95 100 0 5 10 15 20 load curre nt (amps) ef?ciency (%) 400khz 500khz 600khz 0 5 10 15 20 25 60 65 70 75 80 85 90 95 100 load curre nt (amps) ef?ciency (%) 400khz 500khz 600khz 0 5 10 15 20 25 60 65 70 75 80 85 90 95 100 load curre nt (amps) ef?ciency (%) 400khz 500khz 600khz 60 65 70 75 80 85 90 95 100 0 5 10 15 20 load curre nt (amps) ef?ciency (%) 400khz 500khz 600khz ef? ciency vs. load current (vo=1v, vin=12vin, 25c, 100lfm) ef? ciency vs. load current (vo=1.8v, vin=12vin, 25c, 0lfm) ef? ciency vs. load current (vo=1.8v, vin=12vin, 25c, 200lfm) ef? ciency vs. load current (vo=1v, vin=12vin, 25c, 0lfm) ef? ciency vs. load current (vo=1v, vin=12vin, 25c, 200lfm) ef? ciency vs. load current (vo=1.8v, vin=12vin, 25c, 100lfm) oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 12 of 20 www.murata-ps.com/support
typical performance data 60 65 70 75 80 85 90 95 100 0 5 10 15 load curre nt (amps) ef?ciency (%) 400khz 500khz 600khz 60 65 70 75 80 85 90 95 100 0 5 10 15 load curre nt (amps) ef?ciency (%) 400khz 500khz 600khz 60 65 70 75 80 85 90 95 100 0 5 10 15 load curre nt (amps) ef?ciency (%) 400khz 500khz 600khz ef? ciency vs. load current (vo=3.3v, vin=12vin, 25c, 100lfm) ef? ciency vs. load current (vo=3.3v, vin=12vin, 25c, 0lfm) ef? ciency vs. load current (vo=3.3v, vin=12vin, 25c, 200lfm) oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 13 of 20 www.murata-ps.com/support
typical performance data dynamic load transient response: @25c, natural air? ow, vin=12v; input/output capacitance (see table 2.4), data based on the zm di zspm1000 evaluation board. 0a to 12.5a (slew rate 1.0a/s) 12.5a to 25a (slew rate 1.0a/s) 1.0vout 1.8vout 3.3vout oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 14 of 20 www.murata-ps.com/support
overview the murata power solutions oklp-x/25 power block is a non-isolated, switching power converter. it is capable of providing a 49.5w, regulated output of 0.8-3.6v dc, with load currents up to 25a at 1v output voltage. the power block has an input range of 7-13.2v dc. the power block is a synchronous buck converter and has been implemented using a synchro- nous buck gate driver ic with co-packed control and synchronous mosfets and schottky diode. the output ? lter consists of 375nh inductance and 20f capacitance. a regulated +5v supply is required for the gate driver ic within the oklp-x/25 power block. compelling advantages murata power solutions power blocks offer compelling advantages to users seeking ? exibility and ease-of-use, including the following: ? high ef? ciency, high power density (352 w/in3) in a compact footprint (0.5in. x 0.67in.) ? accurate dcr, 5 % tolerance ? accurate temperature sense via precision temp reference ? ease of use; simpler pcb layout; noise/emi contained within power block ? pmbus option (depending on pwm ic used) ? current sharing options (depending on pwm ic used) ? cost between down-solutions and integrated pol modules ? pcb area/bom reduction vs. fully discrete solutions ? compatible with multiple pwm ic suppliers (e.g., ir, linear tech, powervation, ti, zmdi) the ease-of-use aspect of the power blocks enables users to reduce the design cycle to improve time-to-market. the power blocks are a high reliability solution with a calculated mtbf of 3 mh (min.) and service life of 6 years. controlled variances and tight control over the inductor dcr, for example, 5 % tolerance vs. 10%, typically, enables more accurate current sense. in all these variables and features, knowing what you get is important to realizing a successful and reliable design. the oklp-x/25 power block can be used with any analog or digital pwm controller ic. by simplifying the design task and providing for a high-density layout, including a reduced bom (e.g., output capacitance), depending on transient performance vs. output capacitance, the oklp-x/25 power block enables a robust design, reduced total cost of ownership and higher energy ef? ciency across all output load conditions. basic information, including ef? ciency, thermal derating, etc, for the power block alone, not including controller losses, has been characterized. contact murata power solutions for further information. each pin of the power block and related functional information for the controller (pwm) are described. discussion the oklp-x/25 power block is not a completely integrated point-of-load (pol) solution. power blocks comprise the power stage* of a non-isolated converter, integrating the power fets, output inductor, current sense, tem- perature sense, and gate drive circuitry of a synchronous buck converter. this is the part of a pol that performs the heavy lifting in the conversion process. * the power stage of a non-isolated pol: ? does the heavy liftingfets, output inductor, gate drive circuitry ? synchronous buck converter topology (evaluated at 400-600 khz) ? requires external parts for a complete pol solution (pwm, etc.) ? can accommodate analog or digital controllers in order to implement a complete pol solution, external circuitry must be added in the form of a pwm controller, gate drive voltage, as well as input and output capacitors. the power blocks are designed to accommodate either analog or digital pwm controllers, affording customers a wide range of performance features and functionality, according to their needs. for dense pcb circuit implementations, the pwm controller can be mounted on the underside the pcb, resulting in a very dense pcb layout. 25a power block: technical notes figure 6. 25a power block * 0.22f external capacitor must be used for accurate current sense thermal sensor output filter vout gnd +5v vin pwm gnd temp +cs -cs c* 2.15k input/output connections pin # name function 1 vin input voltage for the mosfet 2 enable turn off module (enable < 0.8v), turn on module (enable > 2.0v) 3 +cs positive dcr sense 4 -cs negative dcr sense 5 vo output voltage 6,9 gnd ground for both input and output 7 temperature from temperature sense device on the power block for temperature sensing 8 pwm 3.3v compliant pwm signal to the gate driver 10 +5v bias voltage for gate driver oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 15 of 20 www.murata-ps.com/support
pcb design guidelines guidelines for proper conductor (surface and buried traces, vias, etc.) copper plating, pad sizes, trace widths, spacing, etc., can be found in ipc- 2221a, generic standard on printed circuit board design. please consult this or similar standards when designing pcb layouts for the high-current output from the olkp power blocks or any high-current power supply, taking into consideration, maximum currents, temperature rise and convec- tion and/or conduction cooling of the end-user application. powerblock power pins placing larger vias close to the power pins will improve thermal perfor- mance. connecting each group of power and ground vias together on all inner layers where possible with a copper area will improve heat dissipa tion. via construction and sizing ? via diameter and copper plating thickness affect current carrying capacity. ? increasing outer layer copper thickness will allow thicker via plating thickness. mps uses 3 oz outer layers for 1 oz via plating. ? increased via plating thickness will prevent barrel cracking when board temperature changes to extremes, including re? ow, resulting in improved reliability. the following chart shows that larger diameter vias or thicker copper plating will improve the current carrying capacity. for optimum performance, heavy copper (2 oz or greater) or use of multiple copper layers should be used for all power connections. for higher currents, improved thermal performance and increased reli- ability of the power converter, the following suggestions are recommended: ? multiple vias capable of carrying the current required should be used. two adequately sized vias per amp. is not uncommon. ? vias should be placed as close to power pins as permissible. ? use of thermal reliefs for vias and power pads should be avoided. ? unused inner layer via pads should not be removed. this annular ring reduces the resistance and increases the copper area of the via. con- necting these vias together on as many inner layers as possible using copper ? lls will also improve via performance. ? it is important to note that hole plating thickness and circumference must be used to determine the cross section when calculating the cur- rent carrying capacity of vias. hole plating thickness will be much thinner than the copper weight of the printed circuit board. ipc-2221a formula for calculating trace width and vias i = kt 0.44 a 0.725 where: i = current in amperes a = cross section in sq mils t = temperature rise in c k is a derating constant such that: k = .048 for outer layers k = .024 for inner layers input/output capacitor selection the required amount of input and output capacitance will be determined on an application by application basis. however, there are guidelines common to every design which can be identi? ed and following is a very brief overview. for instance, ceramic capacitors with very low esr (and esl, if pub- lished) should be selected to reduce input and output ripple voltages. these should be placed as close to the power supply input as practical. external input bypass bulk capacitance should then be determined in order to stabilize the input voltage during large load transients and supply extra cur- rent to the load during a step load change. the maximum output capacitive loading speci? ed in the datasheet should be observed. consideration must also be given to ripple voltage and currents and the impact on capacitor lifetime and system reliability. note that both input and output capacitors should be placed close to the load. also, as some systems are dif? cult to fully characterize analytically, some empirical testing may be necessary to assure successful operation. input capacitor selection reduce input ripple voltage: the ? rst step is to reduce ripple voltage amplitude at the input of the converter. for this purpose, ceramic capacitors with very low esr should be selected; large, bulk capacitors do not reduce ripple voltage, as the esr of aluminum electrolytics and most tantalums are too high to allow for effective ripple reduction. therefore, to reduce the rms current in the bulk capacitors the ripple voltage amplitude must be reduced using ceramic capacitors. from the literature, as a general rule of thumb, keeping the peak to peak ripple amplitude below 75 mv keeps the rms currents in the bulk capacitors within acceptable limits. load current, duty cycle, and switching frequency are several factors which determine the magnitude of the input ripple voltage. the input ripple voltage amplitude is directly proportional to the output load current. the maximum input ripple amplitude occurs at maximum output load. also, the amplitude of the voltage ripple varies with the duty cycle of the converter. for a single phase buck regulator, the duty cycle is approximately the ratio of output to input dc voltage. a single phase buck regulator reaches its maximum ripple at 50% duty cycle. further detail can be found in the literature. the following equation can be used to determine the amount of ceramic capacitance required to reduce the ripple voltage amplitude to acceptable levels: t k a = (diameter * pi * plating) i = (k * (t ^ 0.44)) * (a ^ 0.725) via diameter (mils) via wall plating thickness (oz) 1.00 0.50 0.25 10 1.54 a 0.93 a 0.56 a 15 2.06 a 1.25 a 0.75 a 20 2.54 a 1.54 a 0.93 a 25 2.99 a 1.81 a 1.09 a 30 3.41 a 2.06 a 1.25 a 35 3.81 a 2.31 a 1.40 a 40 4.20 a 2.54 a 1.54 a 50 4.94 a 2.99 a 1.81 a 60 5.63 a 3.41 a 2.06 a t = max temperature rise above ambient (25c) k = derating constant (.024) a = area in square mils i = current in amps oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 16 of 20 www.murata-ps.com/support
c min = (iout x dc x (1-dc) x 1000)/(f sw x vpmax), dc=vout/(vin x ? ); ? =ef? ciency where f sw is the switching frequency in khz iout is the steady state output load current c min is the minimum required ceramic input capacitance in f ? vp (max) is the maximum allowed peak-peak ripple voltage ? example ceramic calculation given: ? vin = 12 v ? vout = 3.3 v ? iout = 10 a ?? ? = 90% ? f sw = 333 khz ? dc = 0.3 the minimum ceramic capacitance required to reduce the ripple voltage to 75 mvpp is calculated to be: c min =(10a x 0.3 x (1-0.3) x 1000)/333 x 75mv = 84f ? the actual capacitance of a ceramic is less than the stated nominal value at a given dc voltage. make sure the actual value is equal to or greater than the calculated value. ? 75 mvpp is recommended vpmax. this will yield approximately 22 mvrms of ripple voltage. transients and bulk capacitors bulk capacitors control the voltage deviation at the input when the con- verter is responding to an output load transient. the higher the capacitance, the lower the deviation. therefore, the size of the input bulk capacitor is determined by the size of the output current transient and the allowable input voltage deviation. the amplitude of the input voltage deviation during a transient is directly proportional to the load current change. if the magni- tude of the transient load current is doubled, the input voltage disturbance is doubled also. lower input voltage means higher input currents. the input current scales directly by duty cycle. at lower input voltages the input transient currents will also be higher. to comply with output voltage deviation limits, more input capacitance is required. consider a 2.5v output regulator with a 10a transient load. with a 12v input, the ideal duty cycle is 2.5/12 = 0.208. the 10 a load transient on the output transforms to a 2.08a transient on the input. with a 3.3 v input regulator, the duty cycle is now 2.5/3.3=0.758. the 10 a load transient is now a 7.58a input transient. this will cause a larger voltage deviation on the lower voltage supply where the voltage limits are probably tighter. during a transient, input inductance slows the current slew rate seen by the host supply. the use of a ? lter inductor places more demands on the input bulk capacitors since more of the initial current demand must come from the input capacitors rather than the host supply. the input voltage at the regulator input now sees a much higher voltage deviation. in the end, both the input and output capacitors have to be recharged, causing higher peak currents to be demanded from the host supply. bulk input capacitance calculation example when designing a system consisting of a single pol module, the ? rst step is to calculate the magnitude of the input transient current. this is done by calculating the re? ected input transient for each pol modules output transient. when calculating, you must determine the worst case transient combination of all modules and proceed accordingly. the magnitude of the input current transient is calculated from the fol- lowing equation: delta i in =v out /(v in x ? ) x delta i out , where ?? ? is ef? ciency ? i out is the output transient current ? i in is the input transient current ? v out is the nominal output voltage ? v in is the nominal input voltage the ef? ciency value ? is obtained from the regulator data sheet. use a value from the ef? ciency curve for the particular output voltage and the highest expected output current. next, determine the maximum allowable voltage deviation on the bulk capacitors. this is the maximum allowable dip during the peak transient step that was calculated in step one. the smaller the voltage deviation, the higher the required amount of bulk capacitance. the following equation calculates the minimum required bulk capacitance. c = (1.21 x i 2 in x l)/v 2 where: i in is the change in input current in response to the output step load transient l is stray inductance in the host supply path and/or any series inductor ? v is the allowable input voltage dip following the output step load tran sient note that this equation is an approximation. the value it produces should be considered to be an absolute minimum amount. the exact value will have to be determined through experimentation depending on how well regulated your host supply is. example ? assume ? lter l = 560 nh ? assume allowable v is 100 mv ? assume input transient current (i in ) was calculated to be 2.774a c = (1.21 x i 2 in x l)/v 2 = (1.21 x (2.774) 2 x 560 x 10 -9 )/(-.100) 2 = 521 f according to the calculation, a minimum 521f of bulk capacitance is needed. use the nearest standard value of 560 f. ? the user needs to decide if a series ? lter inductor is going to be used. if using an inductor, pick a value no greater than 560 nh. if not using one, use a value of 50 nh in the calculation to account for stray inductance in the host supply path and its ? nite bandwidth. detailed discussion of the use of an input inductor is beyond the scope of these guidelines, however; if re? ected ripple is a concern, a small (560 nh or less) input inductor can be used. at lower currents, this input inductor can take the form of a power ferrite bead. this is an effective way to con? ne ripple currents to the local input bypass caps. an input inductor can reduce the re? ected ripple current by an order of magnitude. during transient conditions, the use of an input inductor puts larger demands on input bulk capacitors. take care when using input inductors as they will affect input capacitor selection. output capacitor selection there are numerous factors to consider when adding external capacitors to switched-mode power supplies (smps), including noise, startup, esr, sta- bility, pre-bias applications, sense inputs, on/off (remote enable) controls and other topics. most dc-dc applications require external bypass bulk capaci tors as part of the output load. these capacitors supply extra current during a step load change. lower dc voltages used in newer logic devices mean that the voltage margin difference between logic zero and logic one is reduced to hundreds or even tens of millivolts. thus, since even modest power supply noise can cause data errors by exceeding this threshold, these bypass caps are necessary to reduce this dc-dc noise. oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 17 of 20 www.murata-ps.com/support
in addition to the possibility of failed or delayed startup, increasing external capacitance can cause sluggish transient response, possible ringing and instability. the maximum output capacitive load speci? cation is really an indication of acceptable and stable startup performance but with moderated transient response. designing for transient performance when designing for a load transient, the output bulk capacitors and high frequency bypass capacitors determine the response performance and voltage deviation of the regulator. the most important parameters are the magnitude of the load transient (i) and the distributed bus impedance to the load. the selection of the output capacitors is determined by the allowable peak voltage deviation (v). this limit should re? ect the actual requirements, and should not be speci? ed lower than needed. the distribution bus impedance seen by the load is the parameter that determines the peak voltage deviation during a fast transient. the system requires a low impedance bus over all frequencies with adequate bypass capacitors to achieve fast slew rates. if the impedance of the network that supplies the load remains below a maximum impedance, the voltage deviation due to the transient will remain within allowable voltage deviation requirements. it is simply ohms law: v= i x z. keep the magnitude of z below the maximum limit, and the transient voltage deviation will stay within its limits. divide v by the i to determine the maximum allowable impedance, zmax. this is the impedance limit which must be maintained by the output capacitor network for frequencies above which the regulator is effective. to maintain low impedance from the regulator to the load, high frequency, low value ceramic capacitors must be placed very close to the load to minimize the effects of trace inductance while larger value ceramic capacitors can be placed closer to the regulator. transient design example calculating the maximum allowable output impedance, given the following requirements: ? vo = 2.5 v ? output current step from 0.8 a to 12.5 a (i = 11.7 a) ? maximum allowable voltage deviation (v) is 100 mv ? 20 a/sec slew rate. v/i = maximum impedance v/i = 100 mv/11.7 a = 8.55 m selecting four 330 f capacitors with an esr of 25 m would provide an effective esr of 6.25 m and 1320 f of total capacitance. using these capacitors, the actual amplitude of the transient deviation would be about 73 mv (11.7 a 6.25 m). by maintaining the low impedance over the complete frequency range, any high slew rate transient will be achieved. absolute maximum capacitor limits all regulators have an absolute maximum capacitance limit. mps dc-dc converter modules incorporate output short-circuit protection. during startup, the regulator must charge the output capacitance in order to raise the output voltage to its set-point and this current ? ow is in addition to any load current that may be drawn by the application circuit. if there is too much output capacitance, the current demanded from the regulator trips its over-current protection circuit. furthermore, each over-current trip will be followed by further attempts by the regulator to restart. this can result in the regulator entering a perpetual cycle of over-current shutdown. data sheet tables give the maximum allowable output capacitance for each module. if external capacitance is required for stable operation, the minimum value will be listed in the datasheet. recommended capaci- tance is also listed in the datasheet for improved transient performance. the recommended capacitance value will meet a typical v spec at a 50% transient load step. detailed analysis has been performed to allow capacitor limits to be accurately de? ned. by following the capacitor recommendations in the data sheet and selecting capacitors based on your actual operating conditions, a reliable, low-cost power system can be designed. additional explanation can be found at the murata power solutions web page at www.murata-ps.com/data/apnotes/dcan-58.pdf , application note d-can-58, output capacitive load considerations. power block performance the oklp-x/25 power block modules have been tested using controller (pwm) ics under various transient load conditions. contact murata power solutions for further details. power block pin functional descriptions pin #1 (vin): input supply pin, with a range of 7 C 13.2vin (see table 1.1). pin #2 (enable): this provides the host or system controller to the option turn-on/off the module. alternatively, this input can also be tied to vin or the +5v supply to the gate driver, pin 10 (up to 15v). pin #3 (+cs), positive dcr (current) sense and pin #4 (-cs), negative dcr (current) sense: for additional information, please reference the relevant applications notes (www.zmdi.com/zspm1000) for the speci? c controller (pwm) ic to be used. contact murata power solutions for further infor- mation. a brief description of using current sense with the power block follows. current sensing many controller (pwm) ics implement average current sensing to provide accurate current information over the switching period. a generated schematic of the required current sensing circuitry is shown in ? gure 7 for the widely used dcr current-sensing method, which uses the parasitic resistance of the inductor to acquire the current information. the principle is based on a matched time-constant (i.e., rc=l/r (dcr) between the inductor and the low-pass ? lter built from the 2.15k resistor and an exter- nal capacitor (not supplied with the oklp-x/25 power block) across +cs and Ccs (220f), where the inductor l and dcr (+5%) values are used. pin #5 (vout): output voltage supplied to the load. note: there is minimal input/output capacitance incorporated in the power block. approximately 600f is typical at 25a output current level, depending on the application. ref. to paragraph 2.4. capacitor (oklp-x25 datasheet). the user needs to determine the appropriate amount of external capacitance for energy stor- age, ripple voltage requirements, etc. pin #6 (gnd) pin #7 (temperature): temperature measurement the oklp-x/25 includes a thermal sensor in the module for temperature sensing of the inductor. this element is used by the controller for tempera- ture compensation, measuring the inductor temperature. this information oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 18 of 20 www.murata-ps.com/support
can be used to adapt the gain of the current sense path to compensate for the increase in actual dcr. pin #8 (pwm): this is a 3.3v logic level tri-state pwm input and 7v tolerant. high turns the control mosfet on, and low turns the synchronous mosfet on. tri-state turns both mosfets off. in diode emulation mode, tri-state activates internal diode emulation control. pin #10 (+5v): supply to the gate driver ic (4.5v to 7v). this can be sup- plied via another +5v power rail, or a linear regulator or an ldo (e.g., lm317 or lp2992). power block design process the design process begins with selecting a pwm controller for use with the oklp-x/25-w12 power block. as each controller (pwm) ic differs in con? guration and performance, the user needs to ensure that adequate technical support is available from the supplier of choice (e.g., datasheets, application notes, and con? guration tools). for details concerning usage with a power block (i.e., the power stage) to implement a point-of-load solution, including regulation, transient performance, protection, and sequencing, please consult the suppliers web page. contact murata-ps technical support ( www.murata-ps.com/support ), as well as the websites below, for further information. www.zmdi.com/murata_power_block www.powervation.com/products/single-phase-controllers figure 7. inductor current sensing using the dcr method thermal sensor l c vout gnd 2.15k +5v vin pwm gnd +sense - sense temp +cs -cs 0.22f oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 19 of 20 www.murata-ps.com/support
figure 8. typical oklp-x/25-w12 - controller implementation ,6161 ,6163 &*1' 9)%3 9)%1 9,13 &*1' &*1' &*1' &*1' 3*1' 3*1' $''5 $''5 &21752/ 6&/ 6'$ 60%$/(57 3*22' '9'' '9'' 9b6xsso\ 9b6xsso\ 5 8 $*1' 95()3 9)%3 9)%1 ,6163 ,6161 7(03 9,1 $''5 $''5 3:0 /6( 3*22' &21752/ *3,2 60%$/(57 6'$ 6&/ *1' 9'' 9'' 9'' $9'' $'&5() sdg 9,13 5 5 3*1'r 5 5 5 9287 8 2./3;:& 9,1 (qdeoh &6 &6 9287 *1' 7hps 3:0 *1' 9 5 3*1'l /6( 73 oklp-x/25-w12-c 25a power block non-isolated dc-dc converter oklp-x/25-w12-c.a01.d22 page 20 of 20 www.murata-ps.com/support murata power solutions, inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained her ein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci? cations are subject to cha nge without notice. ? 2013 murata power solutions, inc. murata power solutions, inc. 11 cabot boulevard, mans? eld, ma 02048-1151 u.s.a. iso 9001 and 14001 registered this product is subject to the following operating requirements and the life and safety critical application sales policy : refer to: http://www.murata-ps.com/requirements/
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